Generally, Ta.sub.2 O.sub.5 has been considered for use as the dielectric layer of a memory cell capacitor. Ta.sub.2 O.sub.5 has a dielectric constant of 25, which is about 3 to 6 times higher as compared with 3.9 for a silicon dioxide layer and 7.5 for a silicon nitride layer. Therefore, this material is being studied as a substitute material for the stacked structure of silicon nitride/silicon dioxide layers.
That is, with Ta.sub.2 O.sub.5 having a high dielectric constant, the capacitance of a capacitor having a dielectric layer consisting of Ta.sub.2 O.sub.5 can be increased as compared with a capacitor having a dielectric layer consisting of silicon nitride or silicon dioxide. Alternatively, for a given capacitance, the area of the capacitor can be reduced using Ta.sub.2 O.sub.5 as the dielectric layer. For such reasons Ta.sub.2 O.sub.5 has been considered promising for potential use in 64M or 256M DRAMs.
However, Ta.sub.2 O.sub.5 dielectric layers have not been successfully put to practical use at present. A reason for this is that, while the Ta.sub.2 O.sub.5 layer blocks efficiently the movement of electrons, positive holes may move easily in Ta.sub.2 O.sub.5. As a result, leakage current through the Ta.sub.2 O.sub.5 layer can be high.
A conventional technique for lowering the leakage current is focused on annealing after the deposition of the Ta.sub.2 O.sub.5. The most widely used annealing method is a dry-oxidization using a UV-O.sub.3 or O.sub.2 atmosphere. Also, instead of using doped poly-crystalline silicon, TiN has been used in an effort to get better results. In the case of positive bias, however, the reduction of the leakage current has not reached an acceptable value.
FIG. 1 illustrates a partial sectional view of a semiconductor having Ta.sub.2 O.sub.5 layer 23 such as for use in a capacitor. That is, as shown in FIG. 1(A), first polysilicon layer 22, which is used for the first electrode (storage electrode) of the capacitor, is deposited on substrate 21, and then Ta.sub.2 O.sub.5 dielectric layer 23 is deposited. Then, as shown in FIG. 1(B), dielectric layer 23 is dry-oxidized or heat-treated by using a UV-O.sub.3 atmosphere.
Next, the second electrode of the capacitor (not shown) is formed by depositing a conductive material such as doped polysilicon or metal.
The dry-oxidation after depositing Ta.sub.2 O.sub.5 dielectric layer 23 is performed so that oxygen is diffused into Ta.sub.2 O.sub.5 dielectric layer 23' during the heat treatment, so that the internal defects of Ta.sub.2 O.sub.5 dielectric layer 23' may be reduced. In such a case, silicon dioxide is formed between first polysilicon layer 22 (the first electrode) and Ta.sub.2 O.sub.5 dielectric layer 23'. The silicon dioxide film impedes the flow of positive holes, while electrons easily pass by tunneling.
Current leakage is low in a negative direction bias in that the first electrode adjacent to the silicon dioxide is charged to a positive voltage, but the current leakage is increased in a positive direction bias in that the second electrode adjacent to the Ta.sub.2 O.sub.5 layer is charged to a positive voltage, because the electrons can move through the silicon dioxide film by tunneling, and the positive holes can move easily through the Ta.sub.2 O.sub.5 layer. Therefore, there remains a problem in using a Ta.sub.2 O.sub.5 dielectric layer for the capacitor of memory cell.